There is now a need to provide an interface system to accept a high rate of serial data supplied from such sources as satellite receiving systems, weather satellites, commercial communication circuits, and other electronic devices possessing synchronous serial interfaces. These data sources often provide in addition to the information data, two other categories of data and their own synchronous clock signals. A first type of data is called the serial quality data that is used for parity correlation and which is accomplished by a separate quality data clock. The other group of data which is processed simultaneously with the serial data and the quality data is status information usually necessary for manipulating or otherwise checking on the received data. For example, this data can include a frame beginning signal and a frame ending signal.
In most cases, however, the data sources that provide this high speed, multiple kinds of data, supply such data in a broadcast form. Therefore, the receiving station does not have the ability to control the rate, duration, or kind of data being sent. In a particular example, the National Oceanic and Atmospheric Administration, National Environmental Satellite, Data and Information Service presently operates weather satellite data processing systems and facilities. These facilities receive weather data from polar-orbiting TIROS-N and geostationary GOES satellites and must ingest, process, archive and distribute this data. As a result of a much larger source of data being provided at a much larger increase in data speeds, there is a need for updating computer hardware and other processing electronics that have become obsolete in view of the electronics and techniques being used with these new data sources.
In addition, there is also a need for an interface system that has flexible output characteristics. For example, there is a requirement that the information transmitted by satellites and processed by the receiving high speed computers on the Earth be further transformed or modified so that the data can be utilized in various conventional, computer mainframe systems, such as the IBM 4300 series computer systems and also, by minicomputer systems, such as the DEC family of computers. These systems usually utilize a data input architecture called the Digital Equipment Corporation UNIBUS specifications. These specifications are used by, for example, an IBM Device Attachment Control Unit (DACU) and other computer interface control systems. As such, these utilization system input devices, such as the DACU, require that the supplied data be buffered and supplied in predetermined, and prespecified packages of data.
In addition, there is also a need to supply the weather satellite information and other high speed data to other computer systems or to high speed parallel input output interfaces using data ready-acknowledge control signals or other hand-shaking signals.
One known method and apparatus of handling data in interface circuits is by using a conventional First-In-First-Out (FIFO) buffer memory. Examples of such circuits are disclosed in the U.S. Pat. Nos. 4,062,059 to Suzuki et al.; 4,525,673 to Berkowitz; 4,288,860 to Trost; and 4,236,225 to Jansen.
The Suzuki et al patent discloses an information processing system that has a buffer control circuit for detecting the full and empty states of a FIFO stack and produces a "FULL" signal when the memory capacity of the stack is filled. The device of the Suzuki et al patent is primarily used between two Information Processing Systems (IPS) where the first IPS provides program control information for register conditioning and status retrieval.
The Berkowitz patent discloses data acquisition apparatus whose central component is a FIFO buffer 30 which has an input register 34 and an output register 36. A sequence of digital words presented to FIFO buffer 30 are stored in successive locations therein and a logic 32 generates command pulses for advancing the data through the successive addresses from the input register 34 to the output register 36. However, the circuit of the Berkowitz patent is extremely complex and is not very versatile. The FIFO buffer is used for storing command words to accomplish the control and data acquisition tasks for the timely and orderly performance of the circuit. As such, the FIFO buffer is really a sequence buffer. Consequently, because of the inflexibility of this circuitry, the circuit cannot be used for the acquisition of high speed serial data, nor produce the appropriate interfacing signals for the receiving IPS.
The Trost patent discloses a FIFO buffer in which a variable oscillator clocks data from the buffer into a storage subsystem at a relatively slow rate. As the buffer begins to fill, the oscillator frequency is increased to cause the data to be clocked from the buffer and into the storage subsystem at a higher ate. As such, the objective of the circuitry disclosed in the Trost patent is to transfer parallel data words initiated by a requesting device to and from a storage memory via a FIFO buffer. The circuit does not have much flexibility because data cannot be read or written into the FIFO buffer during refresh intervals.
The Jansen et al patent discloses a FIFO memory and also utilizes status signals. The input to the FIFO memory is variable while the output is fixed. However, the design of the circuit limits its flexibility and utilization in extremely high speed broadcasted data environment.
Two other U.S. Pat. Nos. 4,272,829, to Schmidt and 4,314,355 to Leigh disclose interface circuits using interim storage devices. The circuit disclosed in the Schmidt et al patent uses parallel register circuits 102 and 104 that are preceded by plural data buses. The Leighou et al patent discloses a plurality of digital data processors, each being associated with a corresponding channel and each including a storage device with means for sensing the occurence of a synchronizing signal.
Obviously, there are also other interface circuits currently in use. However, none of these circuits provide the capabilities of a flexible output with self generated control signals and an input capability by receiving high speed, broadcasted serial data. In addition, none of these circuits also perform the necessary multiplexing when the supplied data contains different kinds of data that has to be properly interleaved at the appropriate times. Furthermore, because of the broadcast nature of the data, it is also necessary to provide a circuit that can include the timing circuits to make a high speed serial to parallel conversion before the data multiplexing occurs.